Present day memory components such as random access memories (RAM) have become widely available in densities that are much greater than that envisioned only a few years ago. By today's standards, even relatively small memory arrays contain hundreds of thousands or even millions of individual storage cells. The possibility of having one or more defective cells must therefore be assumed by the designer as the size of a memory increases.
It is now commonplace to include circuitry within a memory which can not only detect when a cell has failed but also to replace the failed cell with an operating cell. This capability is even more important in certain applications such as on-chip memory. It would be extremely cost inefficient to have to discard an entire integrated circuit chip because of the failure of a single memory cell in a memory.
In order to provide a repairable memory array, it is common for such memories to be logically divided into segments whereby the segments are independently testable and repairable. Each of the segments may be organized as a set of column clusters and a selectable spare column cluster or slice.
In order to repair a particular segment, it is first necessary to determine which particular cell or bit has failed within it. During a built-in-self-test procedure, each such column returns a data bit value for each test cycle. By examining the data bit value against an expected value, a bit failure can be determined. In the case of a mis-match between the expected value and the actually returned value, the column which provided the bad bit can be identified using the bit position of the failed bit. The failed column can then be replaced by the spare column.
Because of the possibility of more than one column slice failing, the test logic also preferably determines when more than one bit has failed in a given test cycle. This is important because when this condition exists, the memory is in a failure mode which cannot be repaired by a single column slice replacement. In such an instance, a row replacement may have to be made instead.
There are a number of ways to determine the identity of multiple failed columns. One technique would be to run a wire to the test logic for each column and for every segment. This technique is perhaps the most straightforward and works well if there are no more than a few column slices and segments. This is not a problem typically, for example, in a single bit wide array. However, this technique becomes more problematic in cache memories, which may contain data words that are sixty-four, or more bits wide.
Another way is to run a set of wires, such as in a wired-OR bus configuration with a unique non-empty set of wires being asserted to indicate an address for a failed cluster. The number of wires thus required is the smallest integer, N, such that 2.sup.N is greater than the number of column clusters under test. In general, however, such a scheme would not allow detection of a multi-column failure, since the logical OR of the addresses of two or more failed clusters may map to the address of a third, unrelated cluster.
A type of column identification scheme can also be used to indicate a multi-bit failure. In particular, a separate multi-bit failure detection circuit may be included as part of the wired-OR bus used to provide the address of the failing column. For example, if the memory array contains a 64 bit wide data path, the columns can be divided into eight "chunks", having eight bits. Within chunk, eight wires can be run with one wire associated with each column, e.g., with each bit of the data path. Logic within each column then asserts its corresponding wire if its respective bit mis-matches. The logic performs a logical AND operation of each wire with a logical OR operation of the remaining seven wires. The result is then used to pull down a ninth wire which runs across the entire data path in a wired-OR configuration. This ninth wire therefore operates as a partial multi-bit failure detector, because it is pulled down only when a multi-bit failure is detected within one of the chunks of eight. It does not, however detect all possible multi-bit failure situations. In addition, the scheme requires that each chunk of eight bits have a dedicated wire running across at least half of its data path to accommodate the wired-OR pull downs at each bit position within a chunk.
A double level scheme can be implemented in which an AND of each of the wires provided by each chunk is performed with a logical OR of the remaining seven. A subsequent OR of the eight AND operations indicates a multi-bit failure by virtue of a failure in more than one chunk. Other schemes with smaller chunk sizes can also be imagined.
However, all of these schemes require additional data path wires and associated logic which in turn requires significant area and penalties in terms of delay before the error detection operation is complete. They may also complicate the layout of components within the data path, since the address logic for each segment is different, depending upon its position in the array.